Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B520F2048IM64 /LCD /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (REGULAR)UDCTRL 0 (DSC)DSC

UDCTRL=REGULAR

Description

Control Register

Fields

EN

LCD Enable

UDCTRL

Update Data Control

0 (REGULAR): The data transfer is controlled by SW. Transfer is performed as soon as possible

1 (FCEVENT): The data transfer is done at the next event triggered by the Frame Counter

2 (FRAMESTART): The data transfer is done continuously at every LCD frame start

DSC

Direct Segment Control

Links

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